The Chinese Patent No. 201080067067.7 discloses a low voltage, low power memory. The memory cell shows in the FIG. 1, and the memory array in the FIG. 2.
For the Prior art memory array in FIG. 2, the voltages for programming and reading of cell A are listed in the Table I.
TABLE 1CellV (WP)V (WS)V (BL)V (BR)ProgrammingA SW/SB5.5 V2.5 V  0 VFloatingB SW/UB5.5 V2.5 V  2.5 V  FloatingC UW/SB2.5 V0 V0 VFloatingD UW/UB2.5 V0 V2.5 V  FloatingReadA SW/SB1.0 V0 V0 VV SensingB SW/UB1.0 V0 VFloatingFloatingC UW/SB  0 V0 V0 VV SensingD UW/UB  0 V0 VFloatingFloatingSW: Selected Word line,SB: Selected Bit line,UW: Unselected Word line,UB: Unselected Bit line,
As an example, if the Cell B with Row m and Column t has been programmed, and the sequent programming is for the Cell A of Row m and Column s. During the programming of Cell A, the high voltage of Vpp on the WPm causes a high voltage about (Vpp−Vt) at the Grate gmt. Vt is a small voltage difference on the anti-fuse element Cmt of programmed Cell B. The high voltage at the Grate gmt may cause same damage and leakage of the MOS transistor NMt of Cell B, and the reading of Cell B through Sense Amplifier may have some problem.
The above analysis shows the obvious shortage of the prior art.
Since cell B has been programmed, the anti-fuse element is in the condition of conducting.
During the programming of Cell A, the second MOS transistor of Cell B has the operation condition that the gate voltage about 5.5V (i.e. 5.2V), the source voltage and the gain voltage are 2.5V. Therefore, the voltage about 3V is on the gate oxide layer of the second MOS transistor. The damage and degeneration will increase for such MOS transistor, which normally works at the operation voltage of 1.8V or even less.
There is a need in the art for an OTP cell that can achieve improved performance and remedy the deficiencies in the prior art by limiting of the gate voltage of the second MOS transistor.